A high-k dielectric layer has been employed to form a gate insulation layer of a metal oxide semiconductor (MOS) transistor or a dielectric layer of a capacitor where the high-k dielectric layer may have a thin equivalent oxide thickness (EOT) and may reduce leakage current flowing from a gate electrode of the MOS transistor toward a channel region of the MOS transistor, or flowing from an upper electrode of the capacitor toward a lower electrode of the capacitor.
A hafnium oxide layer has been utilized as the gate insulation layer of a MOS transistor or as the dielectric layer of a capacitor. A method of forming a hafnium oxide layer is described, for example, in U.S. Pat. No. 6,348,386 issued to Glimer. However, components included in the hafnium oxide layer may be crystallized at a relatively low temperature of above about 300° C. so that the leakage current may be augmented in the MOS transistor or the capacitor. More specifically, when the hafnium oxide layer is utilized as the gate insulation layer and a gate electrode of doped polysilicon is formed on the hafnium oxide layer, electron mobility in the channel region of the MOS transistor may be decreased due, in part, to the penetration of impurities such as boron (B).
In an attempt to address the above-mentioned phenomenon, a hafnium silicon oxide layer formed by an atomic layer deposition (ALD) process has been developed. The hafnium silicon oxide layer may possess a desirable equivalent oxide thickness as well as desirable insulation properties. A method of forming a hafnium silicon oxide layer using an atomic layer deposition process is described, for example, in U.S. Patent Application Publication No. 2003/232506, Japanese Patent Laid-Open Publication No. 2003-347297, Korean Patent Laid-Open Publication No. 2002-32054 and Korean Patent Laid-Open Publication No. 2001-35736. However, since the hafnium silicon oxide layer may have a low dielectric constant of about 10 to about 15, the hafnium silicon oxide layer may not be suitable for a semiconductor device having a design rule of below about 50 nm.